1. Field of the Invention
The present invention relates to an image reading device and a method of image reading.
2. Description of the Related Art
Generally, in an image reading device, when reading an image printed on an original, the original is irradiated with a light and the light reflected from the original is received in a charged-coupled device (CCD) line image sensor for converting into an analog image signal. Subsequently, the analog image signal is subjected to sampling thereby converting the analog image signal to digital image signal.
FIG. 15 is a schematic diagram of an optical system in a typical image reading device. As shown in FIG. 15, an exposure glass 2 is arranged on the top surface of a housing 1 of the image reading device. An original 3 having an image printed thereon is mounted between the exposure glass 2 and a pressure plate (not shown). The pressure plate presses the original 3 so that the surface of the original 3 with the image (hereinafter, “target surface”) is in close contact with the exposure glass 2. A white standard board 4 is arranged at the left end of the exposure glass 2, from where the image reading device starts reading the image on the original 3. The white standard board 4 is used to obtain a white shading correction image.
The target surface is irradiated with a light from a light source 5. The light reflected from the target surface then sequentially reflects from a first mirror 6, a second mirror 7, and a third mirror 8, and eventually falls on a lens 11. The lens 11 focuses the light on a charged-coupled device (CCD) line image sensor 13 arranged on an image-reading control plate 12.
The light source 5 and the first mirror 6 are mounted on a first carriage 9 that moves back and forth in a sub-scanning direction SS. Similarly, the second mirror 7 and the third mirror 8 are mounted on a second carriage 10 that also moves back and forth in the sub-scanning direction SS. The second carriage 10 moves at half the speed of the first carriage 9 such that the optical path length between the exposure glass 2 and the CCD line image sensor 13 is maintained constant.
A scanner motor 14 moves the first carriage 9 and the second carriage 10.
FIG. 16 is a schematic diagram of a signal processing unit in the image reading device that performs analog to digital conversion of signals output from the CCD line image sensor 13.
First, the CCD line image sensor 13 outputs an analog image signal in synchronization with input of a driving pulse signal. The analog image signal then passes through a buffer circuit 22 (usually, an emitter-follower circuit) to a capacitor 23. The analog image signal is subjected to alternating-current (AC) coupling in the capacitor 23 and then input into an analog integrated circuit application 28, which is an analog front end (AFE).
The analog integrated circuit application 28 includes a clamping circuit 24, a sampling-and-holding circuit (S/H) 25, a programmable gain amplifier (PGA) 26, and an analog-to-digital converter (ADC) 27. In the analog integrated circuit application 28, the clamping circuit 24 receives the AC-coupled analog image signal from the capacitor 23 and clamps a black offset level of the AC-coupled analog image signal to a predetermined voltage in synchronization with input of a clamp signal CLP and outputs the clamped analog image signal.
The sampling-and-holding circuit 25 outputs a continuous analog image signal by sampling the clamped analog image signal in synchronization with input of a sampling-and-holding pulse SHD and holding the sampled analog image signal for a predetermined amount of time. The PGA 26 amplifies the continuous analog image signal to a predetermined signal level and outputs the amplified analog image signal. The ADC circuit 27 then converts the amplified analog image signal into, e.g., a 10-bit digital image signal in synchronization with input of a conversion timing signal ADCLK and outputs the digital image signal to an image processing unit (not shown) arranged subsequently.
Meanwhile, the light source 5 also illuminates the white standard board 4 such that the CCD line image sensor 13 receives the light reflected from the white standard board 4. Based on that, a shading correction circuit (not shown) in the image processing unit obtains a predetermined level of image density and corrects sensitivity fluctuation of the CCD line image sensor 13 or unevenness in the light distribution of the optical system in the image reading device. Moreover, the shading correction circuit also performs digital processing such as gamma correction on the digital image signals.
A timing signal generating circuit 1630 generates various timing signals necessary for driving the CCD line image sensor 13 and the analog integrated circuit application 28 based on an output signal of an oscillator (OSC) 29, and outputs the timing signals to the CCD line image sensor 13 and each circuit in the analog integrated circuit application 28.
The timing signal generating circuit 1630 includes a phase locked loop (PLL) circuit 30a, five signal-dividing and phase-regulating circuits (hereinafter, “phase regulating circuits”) 1630b, 1630c, 1630d, 1630e, and 1630f, and a buffer 30p corresponding to each of the phase regulating circuits.
The PLL circuit 30a performs signal multiplication on the output signal of the oscillator 29 and transmits the multiplied output signal to the phase regulating circuits 1630b, 1630c, 1630d, 1630e, and 1630f. The multiplied output signal is appropriately divided between the phase regulating circuits 1630b, 1630c, 1630d, 1630e, and 1630f for generating necessary timing signals.
More particularly, the phase regulating circuit 1630b generates clock signals φ1 and φ2 used for sampling of an image light in the CCD line image sensor 13, and a timing signal TG. The phase regulating circuit 1630c generates clock signals φ2L and CP used for the signal output from the CCD line image sensor 13, and a reset signal RS. The phase regulating circuit 1630d generates the clamp signal CLP and outputs it to the clamping circuit 24. The phase regulating circuit 1630e generates the sampling-and-holding pulse SHD and outputs it to the sampling-and-holding circuit 25 via the buffer 30p. The phase regulating circuit 1630f generates the conversion timing signal ADCLK and outputs it to the ADC circuit 27.
The clock signals φ1 and φ2 are transfer clock signals for transferring a signal charge obtained from a photodiode array (not shown) in the CCD line image sensor 13 to an analog shift register (not shown) and then performing charge transfer from the analog shift register. The timing signal TG is used for transferring a charge accumulated in the photodiode between two exposure timings to the analog shift register. The reset signal RS is a timing clock signal that initializes a voltage of a floating capacitor (not shown) in a source-follower circuit (not shown) in the CCD line image sensor 13 for outputting the analog image signal, for each pixel of the analog image signal. The clock signal CP is a timing clock signal that determines an internal clamping timing in the CCD line image sensor 13 such that an offset voltage of an output waveform of the CCD line image sensor 13 is set.
A central processing unit (CPU) 1639 controls a timing for driving the CCD line image sensor 13 and phase regulation of the timing signal generating circuit 1630.
FIG. 17 is a circuit diagram of the sampling-and-holding circuit 25. As shown in FIG. 17, the sampling-and-holding pulse SHD from the phase regulating circuit 1630e is input to a signal ON/OFF switch for a capacitor, which holds a sampling value in the sampling-and-holding circuit 25. As shown in FIG. 18, a sampling process (sampling timing) is started at a falling edge of the sampling-and-holding pulse SHD, and the sampling process is finished and a holding process (holding timing) is started at a rising edge thereof.
The process of sampling and holding needs to be performed within an image signal period (ISP) of the analog image signal (CCDOUT) output from the CCD line image sensor 13. More particularly, the holding timing shown in FIG. 18 needs to occur within the image signal period. Moreover, a necessary sampling period (NSP), which the sampling-and-holding circuit 25 requires to perform sampling, also needs to occur within the image signal period.
Usually, the overall sampling period of the sampling-and-holding circuit 25 is longer than the necessary sampling period. Thus, as long as the necessary sampling period is secured, it does not matter whether the sampling timing occurs within the image signal period.
However, as shown in FIG. 19, there is a possibility that the holding timing does not occur within the image signal period due to various reasons. Such a problem can occur, for example, if there is fluctuation in the output delay of the sampling-and-holding pulse SHD at the buffer 30p or fluctuation in a time constant of the transmission line between the phase regulating circuit 1630e and the sampling-and-holding circuit 25. The same problem can also occur if there is fluctuation in the output delay of the driving pulse for the CCD line image sensor 13 at a corresponding buffer (not shown), or fluctuation in a time constant of the transmission line for the CCD line image sensor 13, or fluctuation in the amount of output delay of the analog image signal from the CCD line image sensor 13.
A conventional technology has been disclosed, for example, in Japanese Patent Application Laid-open No. 2000-307852.
If such problems keep on occurring over a period of time, it becomes difficult to secure an optimal holding timing and the necessary sampling period. Moreover, with the advance of high-speed image reading devices, the increase in pixel frequency has resulted in a shorter image signal period. Thus, it has become further difficult to secure the holding timing and the necessary sampling period.
If the holding timing does not occur within the image signal period, a signal level of the sampling-and-holding circuit 25 deviates from an ideal signal level thereby affecting the output of the image reading device and degrading the image quality. Moreover, if a timing-based sampling and holding is performed on an image signal component that has a high degree of fluctuation in the signal level (see FIG. 19), then a signal-to-noise ratio in the image signal output deteriorates thereby resulting in degradation of the image quality.